DDR Ram - What's It Really All About?

CPU clock rates have experienced an exponential growth, leaving the rest of the PC components behind. In the resulting high-end systems, the memory bus constitutes the probably most important bottleneck. Ramping up bandwidth only partially solves the problem since latencies become the primarily important bottleneck. Reducing latencies by means of faster strobes is technically difficult and economically not viable, particularly if the bus speed is increased to approach 200 MHz. Alternative solutions encompass combined SRAM-DRAM solutions that, at minimal overhead, mask latencies by uncoupling data output from the DRAM array. A simple row cache architecture, employing time multiplexed internal buses to load entire rows into centrally located 8 kb SRAM cells, can function as output buffer. Thus, the DRAM array can be precharged ahead of time to avoid page closing latencies as well as refresh penalties